1. Field of the Invention
The present invention relates to a communication control system capable of transmitting data after converting the data transmission speed when the data transmission speeds of a sending system and a receiving system differ.
2. Description of the Related Art
With progress in data communication technology, data are being transmitted at increasing speeds. Thus, development of data communication technology is required to facilitate communication between two systems having different data transmission speeds.
To realize data communication between two systems having different data transmission speeds, there are two conventional methods as shown in FIGS. 1A and 1B.
The first method shown in FIG. 1A is to realize the data communication between two systems (a system A101 and a system B102) having different transmission speeds by converting the transmission speed through a main memory 103 and a buffer memory 104, both provided between the two systems having different data transmission speeds (system A 101 and system B 102).
System A 101 is connected to the buffer memory 104 through a communication line, the buffer memory 104 is connected to the main memory 103 and the main memory 103 is connected to system B 102 through a communication line. Data transmission between system A 101 and the buffer memory 104 is controlled by a DMA controller 105 (DMAC-A) , data transmission between the buffer memory 104 and the main memory 103 is controlled by a CPU 106, and data transmission between the main memory 103 and system B 102 is controlled by a DMA controller 107 (DMAC-B).
In transmitting data from system B 102 to system A 101, data are first transmitted from system B 102 to the main memory 103 under the control of the DMAC-B107. This transmission Tb108 is performed at the data transmission speed of system B 102. Then, the transmission data stored in the main memory 103 are read one by one by the CPU 106 and written in the buffer memory 104. This process is executed by a normal READ/WRITE command of the CPU 106. Finally, the data are transmitted from the buffer memory 104 to system A 101 under the control of the DMAC-A105. This transmission Ta109 is performed at the data transmission speed of system A 101.
On the other hand, in transmitting data from system A 101 to system B 102, the data are first transmitted by DMA from system A 101 to the buffer memory 104 under the control of the DMAC-A 105. Then, the data are read from the buffer memory 104 by the CPU 106, and written to the main memory 103. Finally, the data are transmitted by DMA from the main memory 103 to system B 102 under control of the DMAC-B 107.
As described above, in the first method the main memory 103 and the buffer memory 104 are provided between system A 101 and system B 102 and the transmission between the buffer memory 104 and the main memory 103 is executed by READ/WRITE of the CPU 106, thus absorbing the difference in the transmission speeds of transmission Ta109 of system A 101 and transmission Tb108 of system B 102.
The second method shown in FIG. 1B is to provide a FIFO memory 110 between system A 101 and system B 102. In the FIFO memory 110, the write and read operations must be set to different speeds.
The FIFO memory 110 is controlled by the CPU 106. First, data from system A 101 are written in the FIFO memory 110. This transmission Ta109 is performed at the transmission speed of system A 101. Then, the data written in the FIFO memory 110 are transmitted sequentially to system B 102. This transmission Tb108 is performed at the transmission speed of system B 102.
However, there are problems with both of these methods.
In the first method, data transmitted to the main memory 103 or the buffer memory 104 are read in words by the CPU 106, and then written in the buffer memory 104 or the main memory 103. In this method, the transmission speed is exceedingly low. Besides, as the main memory 103 and the buffer memory 104 are controlled by one CPU 106, the transmission Ta109 of system A 101 and the transmission Tb108 of system B 102 cannot be performed simultaneously, thus further reducing the transmission speed. Furthermore, in this method the memory capacity of both the buffer memory 104 and the main memory 103 must be large. Another problem is that the CPU cannot be operated during a data transmission.
In the second method, as the FIFO memory is used where different input/output speeds are permitted, there is no problem reduction in data transmission speed. However, there is the problem that the FIFO memory is expensive, although it is effective in optionally setting input/output speed.